Power MOSFETs with very low on-state resistance are useful in a number of applications, such as disk drives, automotive electronics and power supplies. In the case of power supplies for VLSI chips, output power rectifiers must support 20 volts to provide a 3.3 volt output. In order to minimize the power loss in such power MOSFETs, these MOSFETs must have as low an on-state resistance as possible and as high an off-state resistance as possible. The on-state and off-state resistances of these devices are determined by the doping concentration, thickness and width of drift regions within which current is conducted. Because the channel resistance is a major part of the total on-state resistance, this resistance must be as small as possible in its on-state and as large as possible in its off-state. Although a power MOSFET with reduced resistance can be produced by increasing its channel width (see for example, U.S. Pat. No. 5,008,725 entitled Plural Polygon Source Pattern For MOSFET issued to Alexander Lidow, et al on Apr. 16, 1991), this is not an attractive approach, because device compactness is also important. Indeed, a standard figure of merit for these devices is the product of the on-state resistance and the die area, because this figure of merit reflects both the compactness and the on-state power loss of this device. Thus, it is a common design goal to produce power MOSFETs having the smallest possible product of on-state resistance and die area.
Power MOSFETs having a reduced product of on-state resistance and device area have been manufactured as trench-based MOSFETs (also referred to as TMOSFETs). In these devices, a plurality of trenches are formed into the top surface of each die to produce a plurality of pedestals on the sidewalls of which are formed the TMOSFETs. The source and drain electrodes are formed on the top and bottom of the die, respectively, so that the electrical current flows from the top surface of the die to its bottom surface.
The article Daisuke Ueda, et al, An Ultra-low On-resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process, IEEE Transactions on Electron Devices, Vol. ED-34, No. 4, April 1987, presents a TMOSFET design and associated manufacturing process. Because technological factors limit the compactness of MOSFETs formed using diffusion fabrication techniques, this paper presents a process and resulting device structure in which the dimensions are defined by the trench, thereby avoiding packing density reductions caused by mask alignment tolerances of multiple mask steps. The resulting TMOSFET is an enhancement type TMOSFET having a conduction MOS channel formed in a p-type body.
In order to avoid parasitic effects at the p-n junction between the source (the top layer of the TMOSFET) and body region (the first layer under the top layer), these two regions are shorted together. This increases the minimum lateral dimension of each pedestal by at least the minimum lateral dimensions of the body portion that penetrates through the source to produce this short, thereby producing a concomitant increase in the area of this device. Because this increased area increases the above-indicated figure of merit of this devices (i.e., the product of the on-state resistance and the die area, which is preferably minimized), this structure has a less favorable figure of merit than desired. The use of a p+ body to achieve this shorting introduces, at the source-body junction, an n+- p+ junction that can cause latchup. The use of a p+ body to achieve this shorting also introduces, at the body-substrate junction, a p +- n junction that conducts carriers like a diode, thereby degrading the bidirectionality of its switching.
The TMOSFET presented in the article B. J. Baliga, T. Syau, and P. Venkatraman, The Accumulation-Mode Field-Effect Transistor: A New Ultralow On-Resistance MOSFET, IEEE Electron Device Letters, Vol. 13, No. 8, August 1992, pp. 427-429 contains n+ source and drain regions in contact with an n- body region (its "body region"). Therefore, because the source and drain regions are doped with the same polarity of charge carriers, the parasitic capacitance at the boundaries between the body region and the drain and source regions will be much smaller than for the TMOSFET presented in the Ueda article discussed above. However, this device exhibits an undesired level of off-state leakage current through these three regions because of the relatively high conductivity of the body regions during an off-state.